Semiconductor power devices are looking for low on-resistance, and fast switching to reduce conduction loss and switching loss. Common semiconductor power switches include metal-oxide semiconductor field-effect transistors (MOSFET), insulated gate bipolar transistors (IGBT) and junction field-effect transistors (JFET).
Taking MOSFET as an example, the U.S. Pat. No. 7,598,567 discloses a power switching semiconductor device with rectifying junction shunts capable of reducing on-resistance (RDS(on)). The above power switching semiconductor device includes a drift layer, a first body region, a second body region, a contactor region, a shunt channel region, a first terminal and a second terminal. The drift layer comprises a first conductivity type. The first body region is adjacent to the drift layer, and comprises a second conductivity type opposite the first conductivity type. The first body region and the drift layer form a P-N junction. The second body region is on the first body region and comprises the second conductivity type. The contact region is adjacent to the first body region and the second body region and comprises the first conductivity type. The shunt channel region extends from the contactor region to the drift layer and between the first body region and the second body region, and comprises the first conductivity type. The first terminal is in electrical contact with the first body region, the second body region and the contactor region. The second terminal is in electrical contact with the drift layer.
For another example, the U.S. Pat. No. 8,377,756 discloses a MOSFET cell formed by self-aligning techniques and capable of attaining low channel resistance. The above MOFSET cell includes a U-shaped well (P-type), two parallel N-type sources formed within the well, and a plurality of N-type source rungs connected to source regions. Between every two N-type source rungs is a P-type body. The above regions are formed on an N-type epitaxial layer and an N-type substrate. A contact extends across and contacts the plurality of N-type source rungs and bodies. A gate oxide layer and a gate contact overlie a leg of a first well and a leg of a second adjacent well, enabling a gate voltage to invert the conductivity responsive of the wells.
Further, the U.S. Pat. No. 8,476,697 discloses a silicon carbide power MOSFET formed by self-aligning techniques. The silicon carbide power MOSFET includes a drain region of a first conductivity type, a base region having a second conductivity type, and a source region adjacent to an upper surface of the base region and having the first conductivity type. The base region includes a channel that extends from the source region through the base region adjacent to a gate interface thereof. The channel comprise a length less than approximately 0.6 μm. The base region comprise a doping concentration of the second conductivity type sufficiently high that the potential barrier at the source end of the channel is not lowered by the voltage applied to the drain.
In addition to the above prior art, the following disclosures may also be referred: the U.S. Pat. Nos. 5,170,231, 6,165,822, 6,221,700, 6,956,238, 8,575,622, 8,395,162, 8,507,986, and 8,610,130; the U.S. Patent Publication No. 2012/0,329,216; and non-patent publications:    1. J. Rozen, A. C. Ahyi, X. Zhu, J. R. Williams, L. C. Feldman, “Scaling Between Channel Mobility And Interface State Density in SiC MOSFETs” IEEE Transactions on Electron Devices, Vol. 58, No. 11, November 2011, pp. 3808-3811;    2. J. Rozen et al. “The Limits of Post Oxidation Annealing in NO” Materials Science Forum Vols. 645-648 (2010) pp. 693-696;    3. C. Bulucea et al. “Threshold Voltage Control in Buried Channel MOSFETs” Solid-State Electronics Vol. 41, No. 9, pp. 1345-1354, 1997;    4. S. Harada et al. “Low On-Resistance in Inversion Channel IEMOSFET Formed on 4H—SiC C-Face Substrate” Proceedings of the 18th International Symposium on Power Semiconductor Devices & IC's, Jun. 4-8, 2006 Naples, Italy;    5. S. Harada et al. “4.3 mOhmcm2, 1100V 4H—SiC Implantation and Epitaxial MOSFET”, Materials Science Forum Vols. 527-529 (2006) pp. 1281-1284;    6. W. E. Wagner et al. “Characterization of Silicon Carbide Epitaxial Channel MOSFETs” IEEE Transactions on Electron Devices, vol. 47, no. 11, November 2000, pp. 2214-2219;    7. Y. K. Sharma et al. “Phosphorous passivation of the SiO2/4H—SiC interface” Solid State Electronics, 68 (2012) pp. 103-107; and    8. C. T. Yen et al. “SiC Epi-Channel Lateral MOSFETs” Materials Science Forum Vols. 778-780 (2014) pp. 927-930.
The on-resistance RDS(on) of MOSFET can written as:
                              R                      DS            ⁡                          (              on              )                                      =                                            L              ch                                      W              ch                                ·                      1                                          μ                n                            ⁢                                                C                  ox                                ⁡                                  (                                                            V                      G                                        -                                          V                      th                                                        )                                                                                        (        1        )            
Where Lch is the channel length, Wch is the channel width, μn is the channel mobility, Cox is the oxide capacitance, VG is the gate voltage, and Vth is the gate threshold voltage.
When a gate dielectric is formed in a silicon carbide MOSFET by thermal oxidation, unreacted carbon may remain at the interface between the gate dielectric and the silicon carbide to form defects such as silicon vacancy, carbon clusters or carbon interstitial, these defects create energy states within the band gap and become acceptor traps or donor traps. In general, the SiC MOSFET used in the power applications is n-channel MOSFET. N-channels are formed by applying positive gate bias and inversing the pwell region. Those acceptor traps exist near the conduction band edge, will capture the electrons, reduce the available carriers can be used to conduct current and the filled acceptor traps will become negatively charged and act as Coulomb scattering centers for the electrons. These two effects significantly reduce the channel mobility of SiC MOSFET and result in a much higher channel resistance compared to SiC MOSFET.
One of the methods for improving the channel resistance is to use post-oxidation annealing in gases such as nitric oxide (NO), nitrous oxide (N2O) or POCl3 to passivate interface traps, so as to improve the channel mobility μn and reduce the on-resistance. Alternatively, one can improve on-resistance by using structures such as rectifying junction shunts as disclosed previously or by reducing the channel length Lch as disclosed in some prior arts and according to Eq.(1). However, reducing the channel length Lch will increase the saturation current of MOSFET due to short channel effect, which will adversely impact the short circuit withstanding time of devices.